Overview
- Demonstrates a systematic process for formal specification and formal testplanning
- Demonstrates effective use of assertions languages beyond the traditional language construct discussions
- No existing books that talk about either formal testplanning or guidelines for creating assertion-based verification IP
Part of the book series: Integrated Circuits and Systems (ICIR)
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About this book
Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.
The guiding principles promoted in this book when creating an assertion-based IP monitor are:
- modularity—assertion-based IP should have a clear separation between detection and action
- clarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations)
A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.
From the Foreword:
Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come."
Andrew Piziali, Sr. Design Verification Engineer
Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology
Author, Functional Verification Coverage Measurement and Analysis
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Keywords
Table of contents (8 chapters)
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Front Matter
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Back Matter
Authors and Affiliations
Bibliographic Information
Book Title: Creating Assertion-Based IP
Authors: Harry D. Foster, Adam C. Krolnik
Series Title: Integrated Circuits and Systems
DOI: https://doi.org/10.1007/978-0-387-68398-0
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2008
Hardcover ISBN: 978-0-387-36641-8Published: 26 November 2007
Softcover ISBN: 978-1-4419-4218-0Published: 19 November 2010
eBook ISBN: 978-0-387-68398-0Published: 24 November 2007
Series ISSN: 1558-9412
Series E-ISSN: 1558-9420
Edition Number: 1
Number of Pages: XVIII, 318
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Electrical Engineering