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Routing Congestion in VLSI Circuits

Estimation and Optimization

  • Book
  • © 2007

Overview

Authors:
  1. Prashant Saxena

    1. Synopsys, Inc., Hillsboro, USA

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    You can also search for this author in PubMed   Google Scholar

  2. Rupesh S. Shelar

    1. Intel Corporation, Hillsboro, USA

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    You can also search for this author in PubMed   Google Scholar

  3. Sachin S. Sapatnekar

    1. University of Minnesota, Minneapolis, USA

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  • Provides an in-depth treatment of routing congestion in VLSI circuits
  • Comprehensively surveys the work done and points to challenges for the future
  • Equips readers with the knowledge to prudently choose an approach that is appropriate to their design goals
  • Includes supplementary material: sn.pub/extras

Part of the book series: Integrated Circuits and Systems (ICIR)

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-xiv
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  2. The Origins of Congestion

    1. Front Matter

      Pages 1-1
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    2. An Introduction to Routing Congestion

      Pages 3-29

  3. The Estimation of Congestion

    1. Front Matter

      Pages 31-31
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    2. Placement-level Metrics for Routing Congestion

      Pages 33-66

    3. Synthesis-level Metrics for Routing Congestion

      Pages 67-94

  5. Back Matter

    Pages 237-248
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Keywords

About this book

With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid “tra?c jams”; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable? It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ?ow.

Authors and Affiliations

  • Synopsys, Inc., Hillsboro, USA

    Prashant Saxena

  • Intel Corporation, Hillsboro, USA

    Rupesh S. Shelar

  • University of Minnesota, Minneapolis, USA

    Sachin S. Sapatnekar

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