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Advances in Hardware Design and Verification

  • Book
  • © 1997

Overview

Editors:
  1. Hon F. Li

    1. Department of Computer Science, Concordia University, Montreal, Canada

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    You can also search for this editor in PubMed   Google Scholar

  2. David K. Probst

    1. Department of Computer Science, Concordia University, Montreal, Canada

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: IFIP Advances in Information and Communication Technology (IFIPAICT)

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Table of contents (20 chapters)

  1. Front Matter

    Pages i-ix
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  2. ASIC/System Hardware Verification at Nortel: A View from the Trenches

    1. ASIC/System Hardware Verification at Nortel: A View from the Trenches

      • A. Silburt
      Pages 1-1

  3. Advanced Processor Verification

    1. Front Matter

      Pages 3-3
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    2. Proving the Correctness of the Interlock Mechanism in Processor Design

      • Xiaoshan Li, Antonio Cau, Ben Moszkowski, Nick Coleman, Hussein Zedan
      Pages 5-22

    3. Verifying Out-of-Order Executions

      • W. Damm, A. Pnueli
      Pages 23-47

    4. Formal Modeling and Validation Applied to a Commercial Coherent Bus: A Case Study

      • Ganesh Gopalakrishnan, Rajnish Ghughal, Ravi Hosabettu, Abdelillah Mokkedem, Ratan Nalumasu
      Pages 48-62

  4. Semantics of Hardware-Description Languages

    1. Front Matter

      Pages 63-63
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    2. An approach to Verilog-VHDL interoperability for synchronous designs

      • Dominique Borrione, Fredrik Vestman, Hakim Bouamama
      Pages 65-87

    3. A Polymodal Semantics for VHDL

      • Subash Shankar, James Slagle
      Pages 88-105

    4. A semantic model for VHDL-AMS

      • Natividad Martínez Madrid, Peter T. Breuer, Carlos Delgado Kloos
      Pages 106-123

  5. Model Checking

    1. Front Matter

      Pages 125-125
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    2. Model Checking without Hardware Drivers

      • Carlos M. Roman, Gary De Palma, Robert Kurshan
      Pages 127-127

    3. Efficient CTL* Model Checking for Analysis of Rainbow Designs

      • W. Visser, H. Barringer, D. Fellows, G. Gough, A. Williams
      Pages 128-145

    4. Symbolic Model Checking for a Discrete Clocked Temporal Logic with Intervals

      • Jürgen Ruf, Thomas Kropf
      Pages 146-163

  6. Decision graphs

    1. Front Matter

      Pages 165-165
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    2. A Parallel Approach to Symbolic Traversal based on Set Partitioning

      • G. Cabodi, P. Camurati, A. Lioy, M. Poncino, S. Quer
      Pages 167-184

    3. Implementation of a Multiple-Domain Decision Diagram Package

      • Stefan Höreth
      Pages 185-202

    4. Using induction and BDDs to model check invariants

      • David Déharbe, Anamaria Martins Moreira
      Pages 203-213

  7. New Verification Technique

    1. Front Matter

      Pages 215-215
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    2. CheckOff-M: Model Checking and Its Role in IP

      • Roger B. Hughes
      Pages 217-217
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Keywords

About this book

CHARM '97 is the ninth in a series of working conferences devoted to the development and use of formal techniques in digital hardware design and verification. This series is held in collaboration with IFIP WG 10.5. Previous meetings were held in Europe every other year.

Editors and Affiliations

  • Department of Computer Science, Concordia University, Montreal, Canada

    Hon F. Li, David K. Probst

Bibliographic Information

  • Book Title: Advances in Hardware Design and Verification

  • Editors: Hon F. Li, David K. Probst

  • Series Title: IFIP Advances in Information and Communication Technology

  • DOI: https://doi.org/10.1007/978-0-387-35190-2

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: IFIP International Federation for Information Processing 1997

  • Hardcover ISBN: 978-0-412-81330-6Published: 31 October 1997

  • eBook ISBN: 978-0-387-35190-2Published: 09 January 2016

  • Series ISSN: 1868-4238

  • Series E-ISSN: 1868-422X

  • Edition Number: 1

  • Number of Pages: IX, 313

  • Topics: Information Storage and Retrieval

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