VLSI-SOC: From Systems to Chips

1. Front Matter

   Pages i-x

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2. Effect of Power Optimizations on Soft Error Rate

   • Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Y. Xie, M. J. Irwin

   Pages 1-20

3. Dynamic Models for Substrate Coupling in Mixed-Mode Systems

   • João M. S. Silva, Luís Miguel Silveira

   Pages 21-37

4. Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs

   • Thomas Hollstein, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner

   Pages 39-54

5. Automated Conversion of SystemC Fixed-Point Data Types

   • Axel G. Braun, Djones V. Lettnin, Joachim Gerlach, Wolfgang Rosenstiel

   Pages 55-72

6. Exploration of Sequential Depth by Evolutionary Algorithms

   • Nicole Drechsler, Rolf Drechsler

   Pages 73-83

7. Validation of Asynchronous Circuit Specifications Using IF/CADP

   • Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani

   Pages 85-100

8. On-Chip Property Verification Using Assertion Processors

   • José Augusto M. Nacif, Claudionor Nunes Coelho Jr., Harry Foster, Flávio Miana de Paula, Edjard Mota, Márcia Roberta Falcão Mota et al.

   Pages 101-117

9. Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems

   • Jürgen Becker, Michael Hübner, Michael Ullmann

   Pages 119-132

10. A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications

    • Giuseppe Bonfini, Andrea S. Brogna, Roberto Saletti, Cristian Garbossa, Luca Colombini, Maurizio Bacci et al.

    Pages 133-147

11. Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans

    • Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner

    Pages 149-164

12. Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures

    • Alexandre M. Amory, Leandro A. Oliveira, Fernando G. Moraes

    Pages 165-179

13. Optimizing SOC Test Resources Using Dual Sequences

    • Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz

    Pages 181-196

14. A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits

    • Cristiano Lazzari, Cristiano Domingues, José Güntzel, Ricardo Reis

    Pages 197-211

15. Low Power Java Processor for Embedded Applications

    • Antonio Carlos S. Beck, Luigi Cairo

    Pages 213-228

16. Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes

    • Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel

    Pages 229-245

17. Evaluation Methodology for Single Electron Encoded Threshold Logic Gates

    • Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis

    Pages 247-262

18. Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath

    • Jürgen Becker, Alexander Thomas, Maik Scheer

    Pages 263-279

19. Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths

    • Eduardo A. C. da Costa, Jose C. Monteiro, Sergio Bampi

    Pages 281-297

20. Stuck-At-Fault Testability of SPP Three-Level Logic Forms

    • Valentina Ciriani, Anna Bernasconi, Rolf Drechsler

    Pages 299-313

This book contains extended and revised versions of the best papers that have been presented during the twelfth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a Global System-on-a-Chip Design & CAD Conference. The 12* edition was held at the Lufthansa Training Center in Seeheim-Jugenheim, south of Darmstadt, Germany (December 1-3, 2003). Previous conferences have taken place in Edinburgh (81), Trondheim (83), Tokyo (85), Vancouver (87), Munich (89), Edinburgh (91), Grenoble (93), Tokyo (95), Gramado (97), Lisbon (99)andMontpellier(01). The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5, is to provide a forum to exchange ideas and show research results in the field of microelectronics design. The current trend toward increasing chip integration brings about exhilarating new challenges both at the physical and system-design levels: this conference aims to address these exciting new issues. The 2003 edition of VLSI-SoC conserved the traditional structure, which has been successful in previous editions. The quality of submissions (142 papers) made the selection process difficult, but finally 57 papers and 14 posters were accepted for presentation in VLSI-SoC 2003. Submissions came from Austria, Bulgaria, Brazil, Canada, Egypt, England, Estonia, Finland, France, Germany, Greece, Hungary, India, Iran, Israel, Italy, Japan, Korea, Malaysia, Mexico, Netherlands, Poland, Portugal, Romania, Spain, Sweden, Taiwan and the United States of America. From 57 papers presented at the conference, 18 were selected to have an extended and revised version included in this book.

• CMOS
• OFDM
• SystemC
• architecture
• configuration
• optimization
• system on chip (SoC)
• testing

• Technische Universität, Darmstadt, DE

  Manfred Glesner, Leandro Indrusiak, Hans Eveking

• Universidade Federal do Rio Grande do Sul, BR

  Ricardo Reis

• Georgia Tech, USA

  Vincent Mooney

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