Overview
- Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect
- Provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits
- Includes supplementary material: sn.pub/extras
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Table of contents (9 chapters)
Keywords
About this book
Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.
The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Authors and Affiliations
Bibliographic Information
Book Title: Interconnect Noise Optimization in Nanometer Technologies
Authors: Mohamed A. Elgamel, Magdy A. Bayoumi
DOI: https://doi.org/10.1007/0-387-29366-3
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2006
Hardcover ISBN: 978-0-387-25870-6Published: 21 November 2005
Softcover ISBN: 978-1-4419-3844-2Published: 29 October 2010
eBook ISBN: 978-0-387-29366-0Published: 20 March 2006
Edition Number: 1
Number of Pages: XIX, 137
Topics: Circuits and Systems, Computer Hardware, Computer-Aided Engineering (CAD, CAE) and Design, Electrical Engineering