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Leakage in Nanometer CMOS Technologies

  • Book
  • © 2006

Overview

Authors:
  1. Siva G. Narendra

    1. Tyfone, Inc., USA

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    You can also search for this author in PubMed   Google Scholar

  2. Anantha Chandrakasan

    1. Massachusetts Institute of Technology, USA

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    You can also search for this author in PubMed   Google Scholar

  • Each chapter is written by a different combination of experts on the subjects
  • Includes supplementary material: sn.pub/extras

Part of the book series: Integrated Circuits and Systems (ICIR)

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Table of contents (12 chapters)

  1. Front Matter

    Pages i-x
    Download chapter PDF

  2. Taxonomy of Leakage: Sources, Impact, and Solutions

    Pages 1-19

  3. Leakage Dependence on Input Vector

    • Siva Narendra, Yibin Ye, Shekar Borkar, Vivek De, Anantha Chandrakasan
    Pages 21-39

  4. Power Gating and Dynamic Voltage Scaling

    • Benton Calhoun, James Kao, Anantha Chandrakasan
    Pages 41-75

  5. Methodologies for Power Gating

    • Kimiyoshi Usami, Takayasu Sakurai
    Pages 77-104

  6. Body Biasing

    • Tadahiro Kuroda, Takayasu Sakurai
    Pages 105-140

  7. Process Variation and Adaptive Design

    • Siva Narendra, James Tschanz, James Kao, Shekar Borkar, Anantha Chandrakasan, Vivek De
    Pages 141-162

  8. Memory Leakage Reduction

    • Takayuki Kawahara, Kiyoo Itoh
    Pages 163-199

  9. Active Leakage Reduction and Multi-Performance Devices

    • Siva Narendra, James Tschanz, Shekar Borkar, Vivek De
    Pages 201-209

  10. Impact of Leakage Power and Variation on Testing

    • Ali Keshavarzi, Kaushik Roy
    Pages 211-233

  11. Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors

    • Masayuki Miyazaki, Hiroyuki Mizuno, Takayuki Kawahara
    Pages 235-255

  12. Case Study: Leakage Reduction in the Intel Xscale Microprocessor

    • Lawrence Clark
    Pages 257-280

  13. Transistor Design to Reduce Leakage

    • Sagar Suthram, Siva Narendra, Scott Thompson
    Pages 281-299

  14. Back Matter

    Pages 301-307
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Keywords

About this book

Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers.

Authors and Affiliations

  • Tyfone, Inc., USA

    Siva G. Narendra

  • Massachusetts Institute of Technology, USA

    Anantha Chandrakasan

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