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CMOS PLL Synthesizers: Analysis and Design

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  • © 2005

Overview

Authors:
  1. Keliu Shu
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  2. Edgar Sánchez-Sinencio
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  • Offers a complete coverage of both fundamentals and the state-of-the-art design and analysis techniques of PLL synthesizer

Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 783)

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Table of contents (9 chapters)

  1. Front Matter

    Pages i-xvi
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  2. Introduction

    Pages 1-6

  3. Frequency Synthesizer for Wireless Applications

    Pages 7-29

  4. PLL Frequency Synthesizer

    Pages 31-68

  5. ΣΔ Fractional-N PLL Synthesizer

    Pages 69-101

  6. Enhanced Phase Switching Prescaler

    Pages 103-125

  7. Loop Filter with Capacitance Multiplier

    Pages 127-150

  8. Other Building Blocks of PLL

    Pages 151-182

  9. Prototype Measurement Results

    Pages 183-194

  10. Conclusions

    Pages 195-197

  11. Back Matter

    Pages 199-215
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Keywords

About this book

Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.

Bibliographic Information

  • Book Title: CMOS PLL Synthesizers: Analysis and Design

  • Authors: Keliu Shu, Edgar Sánchez-Sinencio

  • Series Title: The Springer International Series in Engineering and Computer Science

  • DOI: https://doi.org/10.1007/b102174

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer-Verlag US 2005

  • Hardcover ISBN: 978-0-387-23668-1Published: 12 November 2004

  • Softcover ISBN: 978-1-4419-3650-9Published: 08 December 2010

  • eBook ISBN: 978-0-387-23669-8Published: 20 January 2006

  • Series ISSN: 0893-3405

  • Edition Number: 1

  • Number of Pages: XVI, 216

  • Number of Illustrations: 85 b/w illustrations

  • Topics: Electrical Engineering

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