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Verification by Error Modeling

Using Testing Techniques in Hardware Verification

  • Book
  • © 2003

Overview

Authors:
  1. Katarzyna Radecka

    1. Concordia University, Canada

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    You can also search for this author in PubMed   Google Scholar

  2. Zeljko Zilic

    1. McGill University, Canada

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    You can also search for this author in PubMed   Google Scholar

Part of the book series: Frontiers in Electronic Testing (FRET, volume 25)

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Table of contents (8 chapters)

  1. Front Matter

    Pages i-xv
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  2. Introduction

    Pages 1-17

  3. Boolean Function Representations

    Pages 18-50

  4. Don’t Cares and Their Calculation

    Pages 51-69

  5. Testing

    Pages 71-102

  6. Design Error Models

    Pages 103-128

  7. Design Verification by At

    Pages 129-146

  8. Identifying Redundant Gate and Wire Replacements

    Pages 147-186

  9. Conclusions and Future Work

    Pages 187-190

  10. Back Matter

    Pages 191-216
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Keywords

About this book

1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be “imminently doable” by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.

Reviews

From the reviews:

"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)

Authors and Affiliations

  • Concordia University, Canada

    Katarzyna Radecka

  • McGill University, Canada

    Zeljko Zilic

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