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Table of contents (8 chapters)
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Front Matter
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Background On Parasitic-Aware Optimization
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Back Matter
Keywords
About this book
In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much, or more, by interconnectg characteristics than by active device properties. In any event, the co-integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed-signal design techniques are employed, parasitics associated with passive elements (resistors, capacitors, inductors, transformers, pads, etc.) and the package effectively de-tune RF circuits rendering them sub-optimal or virtually useless. Hence, dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic-aware RF circuit synthesis techinques described in this book effectively address this critical problem.
Authors and Affiliations
Bibliographic Information
Book Title: Parasitic-Aware Optimization of CMOS RF Circuits
Authors: David J. Allstot, Kiyong Choi, Jinho Park
DOI: https://doi.org/10.1007/b101853
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 2003
Hardcover ISBN: 978-1-4020-7399-1Published: 28 February 2003
Softcover ISBN: 978-1-4757-7754-3Published: 31 May 2013
eBook ISBN: 978-0-306-48129-1Published: 02 December 2005
Edition Number: 1
Number of Pages: XVII, 162
Number of Illustrations: 28 b/w illustrations