Design for AT-Speed Test, Diagnosis and Measurement

1. Front Matter

   Pages i-xvii

   PDF

2. Technology Overview

   Pages 1-33

3. Memory Test and Diagnosis

   Pages 35-57

4. Logic Test and Diagnosis

   Pages 59-92

5. Embedded Test Design Flow

   Pages 93-115

6. Hierarchical Core Test

   Pages 117-137

7. Test and Measurement for PLLs and ADCs

   Pages 139-169

8. System Test and Diagnosis

   Pages 171-187

9. System Reuse of Embedded Test

   Pages 189-216

10. Back Matter

    Pages 217-239

    PDF

Design for AT-Speed Test, Diagnosis and Measurement is the first book to offer practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design makes this book a `must read' before any DFT is attempted.

• development
• diagnosis
• drift transistor
• logic
• system design

• Logic Vision, Inc., USA

  Benoit Nadeau-Dostie

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