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Electromigration Modeling at Circuit Layout Level

  • Book
  • © 2013

Overview

Authors:
  1. Cher Ming Tan

    1. , School of Electrical and Electronic Engr, Nanyang Technological University, Singapore, Singapore

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  2. Feifei He

    1. Nanyang Technological University, Singapore, Singapore

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    You can also search for this author in PubMed   Google Scholar

  • Highlights a new method which models the interconnects EM reliability in both 3D and circuit layout level
  • Combines Cadence and ANSYS softwares to model interconnect reliability of real 3D circuit made up of complete interconnect structures and surrounding materials
  • Compares the circuit EM lifetime with different interconnect structures, surrounding materials, circuit layout and process variations
  • Includes supplementary material: sn.pub/extras

Part of the book series: SpringerBriefs in Applied Sciences and Technology (BRIEFSAPPLSCIENCES)

Part of the book sub series: SpringerBriefs in Reliability (SBR)

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Table of contents (5 chapters)

  1. Front Matter

    Pages i-x
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  2. Introduction

    • Cher Ming Tan, Feifei He
    Pages 1-6

  3. 3D Circuit Model Construction and Simulation

    • Cher Ming Tan, Feifei He
    Pages 7-47

  4. Comparison of EM Performances in Circuit and Test Structures

    • Cher Ming Tan, Feifei He
    Pages 49-74

  5. Interconnect EM Reliability Modeling at Circuit Layout Level

    • Cher Ming Tan, Feifei He
    Pages 75-99

  6. Concluding Remarks

    • Cher Ming Tan, Feifei He
    Pages 101-103
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Keywords

About this book

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.

Authors and Affiliations

  • , School of Electrical and Electronic Engr, Nanyang Technological University, Singapore, Singapore

    Cher Ming Tan

  • Nanyang Technological University, Singapore, Singapore

    Feifei He

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