Multicore Systems On-Chip: Practical Software/Hardware Design

1. Front Matter

   Pages i-xxvi

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2. Introduction to Multicore Systems On-Chip

   • Abderazek Ben Abdallah

   Pages 1-17

3. Multicore SoCs Design Methods

   • Abderazek Ben Abdallah

   Pages 19-35

4. Multicore SoC Organization

   • Abderazek Ben Abdallah

   Pages 37-63

5. 2D Network-on-Chip

   • Abderazek Ben Abdallah

   Pages 65-88

6. 3D Network-on-Chip

   • Abderazek Ben Abdallah

   Pages 89-125

7. Network Interface Architecture and Design for 2D/3D NoCs

   • Abderazek Ben Abdallah

   Pages 127-152

8. Parallelizing Compiler for Single and Multicore Computing

   • Abderazek Ben Abdallah

   Pages 153-173

9. Power Optimization Techniques for Multicore SoCs

   • Abderazek Ben Abdallah

   Pages 175-193

10. Soft-Core Processor for Low-Power Embedded Multicore SoCs

    • Abderazek Ben Abdallah

    Pages 195-213

11. Dual-Execution Processor Architecture for Embedded Computing

    • Abderazek Ben Abdallah

    Pages 215-242

12. Case Study: Deign of Embedded Multicore SoC for Biomedical Applications

    • Abderazek Ben Abdallah

    Pages 243-262

13. Back Matter

    Pages 263-273

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System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device’s functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processingcores and that load balancing between processing cores – especially heterogeneous cores – is very difficult.

• Multicore SoCs Architectures
• Multicore SoCs Design Methodology
• Multicore Systems Programming
• Multicore Systems-on-Chip (SoCs)
• Reconfigurable Multicore SoCs

• , Adaptive Systems Laboratory, University of Aizu, Aizuwakamatsu, Japan

  Abderazek Ben Abdallah

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