Overview
- This is the first comprehensive book on Adiabatic Logic systems
- It presents how Adiabatic Logic will perform with future scaling, future devices and degrading effects
- It presents measurement results of a manufactured adiabatic system and compares it to static CMOS
- Design methodology is presented to generate more energy efficient and less area consuming adiabatic digital signal processing units
- Includes supplementary material: sn.pub/extras
Part of the book series: Springer Series in Advanced Microelectronics (MICROELECTR., volume 34)
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Table of contents (8 chapters)
Keywords
About this book
Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.
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Bibliographic Information
Book Title: Adiabatic Logic
Book Subtitle: Future Trend and System Level Perspective
Authors: Philip Teichmann
Series Title: Springer Series in Advanced Microelectronics
DOI: https://doi.org/10.1007/978-94-007-2345-0
Publisher: Springer Dordrecht
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media B.V. 2012
Hardcover ISBN: 978-94-007-2344-3Published: 30 October 2011
Softcover ISBN: 978-94-007-3727-3Published: 29 November 2013
eBook ISBN: 978-94-007-2345-0Published: 29 October 2011
Series ISSN: 1437-0387
Series E-ISSN: 2197-6643
Edition Number: 1
Number of Pages: XVIII, 166
Topics: Electronic Circuits and Devices, Circuits and Systems, Logic Design, Electronics and Microelectronics, Instrumentation, Energy Efficiency