Authors:
- This book addresses several fundamental design challenges in high-level synthesis of high-performance VLSI System-on-Chip circuits in advanced CMOS technologies
- Some of the main selling points of the book that distinguishes it from other books on High-Level Synthesis include: Currently no other books are available in the market that address interconnect-centric high-level synthesis approaches
- Much of the literature available on this topic are in the form of journal and conference papers
- This book brings together this body of work in a single book that is accessible to VLSI researchers and designers
- This is the first book to describe layout-aware high-level synthesis techniques for the emerging three-dimensional integrated circuit technology
- This is the first book to address signal crosstalk mitigation techniques within a high-level synthesis framework
- This book proposes an integrated approach to power and thermal management during high-level synthesis, to address the growing concerns of high on-chip temperatures in modern high-performance VLSI circuits in nanometer-CMOS technologies
About this book
The exponential scaling in CMOS transistor sizes over the past three decades have enabled spectacular advances in integrated circuit technology, allowing the integration of more than a billion transistors in modern very large-scale integrated (VLSI) circuits. Over the last four decades, transistor scaling has followed Moore's law, and according to projections made by the International Technology Roadmap for Semiconductors (ITRS), minimum feature sizes are expected to reach 22nm by 2012. The primary drivers for transistor scaling are the associated benefits of lower system costs, improved performance, and system reliability.
However, continuous device and interconnect scaling trends in deep submicron designs have created new challenges for integrated circuit designers such as increased interconnect delays due to rising parasitic resistance and capacitance of on-chip wiring, increased on-chip power densities, and performance and reliability problems posed by on-chip thermal gradients and thermal-hotspots. Thus, the major challenge is in achieving reliable, high-performance system implementations, all the way from the micro-architecture level down to the layout level. In order to realize such an implementation, a unified physical-level and high-level synthesis method becomes paramount, to ensure predictability of HLS design flows and minimize design iterations.
Keywords
- Algorithms
- CAD
- High-Level Synthesis
- Nanometer CMOS Technologies
- System-on-Chip
- VLSI
Bibliographic Information
Book Title: Interconnect and Temperature Aware Unified Physical and High Level Synthesis
Authors: Vyas Krishnan, Srinivas Katkoori
Publisher: Springer Dordrecht
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Nature B.V. 2026
Hardcover ISBN: 978-94-007-1892-0Due: 12 November 2025
eBook ISBN: 978-94-007-1893-7Due: 12 November 2025
Edition Number: 1