VLSI Physical Design: From Graph Partitioning to Timing Closure

Authors: Kahng, A.B., Lienig, J., Markov, I.L., Hu, J.

  • Offers comprehensive coverage of Physical Design of Integrated Circuits, PCBs and MCMs, and emphasizes practical algorithms and methodologies Includes a chapter on timing closure that includes a discussion of design flows Features detailed illustrations of key concepts, numerous examples Presents brief surveys of recent research results with up-to-date references for further reading Accessible to beginners and students Includes problem sets for students, with solutions

Buy this book

eBook $59.99
price for USA (gross)
  • ISBN 978-90-481-9591-6
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $79.95
price for USA
  • ISBN 978-90-481-9590-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $79.95
price for USA
  • ISBN 978-94-007-9020-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
About this Textbook

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. VLSI Physical Design: From Graph Partitioning to Timing Closure introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

Reviews



“This book covers the basic algorithms underlying all physical design steps and also shows how they are applied to current instances of the design problems. It will serve the EDA and design community well. It will be a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools.” (Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Corp)

“A clear sign of when a field matures is the availability of a widely accepted textbook. Finally, there is a well-balanced textbook that introduces the key components of a layout synthesis flow with sufficient depth and an eye for the context in which they are used. It lucidly presents what any maker of chip design tools should have as a core foundation.” (Prof. Ralph H.J.M. Otten, Technical University of Eindhoven)

“This is the book I wish I had when I taught EDA in the past, and the one I'm using from now on.” (Dr. Louis K. Scheffer, Howard Hughes Medical Institute)

“I would happily use this book when teaching Physical Design. I know of no other work that's as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed!” (Prof. John P. Hayes, University of Michigan)

“The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure.” (Prof. Kurt Keutzer, University of California, Berkeley)

“An excellent balance of the basics and more advanced concepts, presented by top experts in the field.” (Prof. Sachin Sapatnekar, University of Minnesota)

Table of contents (8 chapters)

Buy this book

eBook $59.99
price for USA (gross)
  • ISBN 978-90-481-9591-6
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $79.95
price for USA
  • ISBN 978-90-481-9590-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $79.95
price for USA
  • ISBN 978-94-007-9020-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
Loading...

Recommended for you

Loading...

Bibliographic Information

Bibliographic Information
Book Title
VLSI Physical Design: From Graph Partitioning to Timing Closure
Authors
Copyright
2011
Publisher
Springer Netherlands
Copyright Holder
Springer Science+Business Media B.V.
eBook ISBN
978-90-481-9591-6
DOI
10.1007/978-90-481-9591-6
Hardcover ISBN
978-90-481-9590-9
Softcover ISBN
978-94-007-9020-9
Edition Number
1
Number of Pages
XI, 310
Topics