Transactions on High-Performance Embedded Architectures and Compilers

Transactions on High-Performance Embedded Architectures and Compilers III

Editors: Stenström, Per (Ed.)

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About this book

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This third issue contains 14 papers carefully reviewed and selected out of numerous submissions and is divided into four sections. The first section contains the top four papers from the Third International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, in January 2008. The second section consists of four papers from the 8th MEDEA Workshop held in conjunction with PACT 2007 in Brasov, Romania, in September 2007. The third section  contains two regular papers and the fourth section provides a snapshot from the First Workshop on Programmability Issues for Multicore Computers, MULTIPROG, held in conjunction with HiPEAC 2008.

Table of contents (15 chapters)

  • Dynamic Cache Partitioning Based on the MLP of Cache Misses

    Moreto, Miquel (et al.)

    Pages 3-23

  • Cache Sensitive Code Arrangement for Virtual Machine

    Lin, Chun-Chieh (et al.)

    Pages 24-42

  • Data Layout for Cache Performance on a Multithreaded Architecture

    Sarkar, Subhradyuti (et al.)

    Pages 43-68

  • Improving Branch Prediction by Considering Affectors and Affectees Correlations

    Sazeides, Yiannakis (et al.)

    Pages 69-88

  • Eighth MEDEA Workshop

    Bartolini, Sandro (et al.)

    Pages 91-92

Buy this book

eBook $69.99
price for USA (gross)
  • ISBN 978-3-642-19448-1
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover $99.00
price for USA
  • ISBN 978-3-642-19447-4
  • Free shipping for individuals worldwide
  • Online orders shipping within 2-3 days.
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Bibliographic Information

Bibliographic Information
Book Title
Transactions on High-Performance Embedded Architectures and Compilers III
Editors
  • Per Stenström
Series Title
Transactions on High-Performance Embedded Architectures and Compilers
Series Volume
6590
Copyright
2011
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer Berlin Heidelberg
eBook ISBN
978-3-642-19448-1
DOI
10.1007/978-3-642-19448-1
Softcover ISBN
978-3-642-19447-4
Series ISSN
1864-306X
Edition Number
1
Number of Pages
XIV, 299
Number of Illustrations and Tables
105 b/w illustrations, 66 illustrations in colour
Topics