Transactions on High-Performance Embedded Architectures and Compilers

Transactions on High-Performance Embedded Architectures and Compilers I

Editors: Editor-in-chief: Stenström, Per
O'Boyle, M., Bodin, F., Cintra, M., McKee, S.A. (Eds.)

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Table of contents (21 chapters)

  • High Performance Processor Chips

    Wilkes, Maurice V.

    Pages 1-4

  • High-Performance Embedded Architecture and Compilation Roadmap

    Bosschere, Koen (et al.)

    Pages 5-29

  • Introduction to Part 1

    Stenström, Per

    Pages 33-33

  • Quick and Practical Run-Time Evaluation of Multiple Program Optimizations

    Fursin, Grigori (et al.)

    Pages 34-53

  • Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems

    Geiger, Michael J. (et al.)

    Pages 54-73

Buy this book

eBook $79.99
price for USA (gross)
  • ISBN 978-3-540-71528-3
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover $109.00
price for USA
  • ISBN 978-3-540-71527-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Transactions on High-Performance Embedded Architectures and Compilers I
Editors
  • Per Stenström
  • Mike O'Boyle
  • Francois Bodin
  • Marcelo Cintra
  • Sally A. McKee
Series Title
Transactions on High-Performance Embedded Architectures and Compilers
Series Volume
4050
Copyright
2007
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag Berlin Heidelberg
eBook ISBN
978-3-540-71528-3
DOI
10.1007/978-3-540-71528-3
Softcover ISBN
978-3-540-71527-6
Series ISSN
1864-306X
Edition Number
1
Number of Pages
XVI, 368
Topics