Skip to main content
SpringerLink
Log in
SpringerLink
Log in

Reconfigurable Computing: Architectures, Tools and Applications

Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings

  • Conference proceedings
  • © 2007

Overview

Editors:
  1. Pedro C. Diniz
    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  2. Eduardo Marques
    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  3. Koen Bertels
    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  4. Marcio Merino Fernandes
    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  5. João M. P. Cardoso
    View editor publications

    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 4419)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: ARC 2007.

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (38 papers)

  1. Front Matter

    Download chapter PDF

  2. Architectures [Regular Papers]

    1. Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array

      • Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev
      Pages 1-13

    2. A Configurable Multi-ported Register File Architecture for Soft Processor Cores

      • Mazen A. R. Saghir, Rawan Naous
      Pages 14-25

    3. MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture

      • Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic
      Pages 26-38

    4. Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture

      • Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho
      Pages 39-48

    5. Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs

      • Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
      Pages 49-60

    6. Systematic Customization of On-Chip Crossbar Interconnects

      • Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis
      Pages 61-72

    7. Authentication of FPGA Bitstreams: Why and How

      • Saar Drimer
      Pages 73-84

  3. Architectures [Short Papers]

    1. Design of a Reversible PLD Architecture

      • Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song
      Pages 85-90

    2. Designing Heterogeneous FPGAs with Multiple SBs

      • Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis
      Pages 91-96

  4. Mapping Techniques and Tools [Regular Papers]

    1. Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations

      • Joonseok Park, Pedro C. Diniz
      Pages 97-109

    2. Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware

      • Yazhuo Dong, Yong Dou, Jie Zhou
      Pages 110-121

    3. Adapting and Automating XILINX’s Partial Reconfiguration Flow for Multiple Module Implementations

      • Rainer Scholz
      Pages 122-129

    4. A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions

      • Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis
      Pages 130-141

    5. Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping

      • Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
      Pages 142-154

    6. The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining

      • Yong Dou, Jinhui Xu, Guiming Wu
      Pages 155-166

    7. Hardware/Software Codesign for Embedded Implementation of Neural Networks

      • Cesar Torres-Huitzil, Bernard Girau, Adrien Gauffriau
      Pages 167-178

    8. Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues

      • João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis
      Pages 179-190

  5. Mapping Techniques and Tools [Short Papers]

    1. About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations

      • Nicolas Hervé, Daniel Ménard, Olivier Sentieys
      Pages 191-200

  6. Arithmetic [Regular Papers]

    1. Switching Activity Models for Power Estimation in FPGA Multipliers

      • Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena
      Pages 201-213
Back to top

Other volumes

  1. Reconfigurable Computing: Architectures, Tools and Applications

Keywords

Bibliographic Information

Publish with us

Policies and ethics

Back to top

Search

Navigation