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Hardware IP Security and Trust

Editors: Mishra, Prabhat, Bhunia, Swarup, Tehranipoor, Mark (Eds.)

  • Discusses security and trust issues throughout the SoC life-cycle, including adversaries and attack surfaces, threat models and instances
  • Provides design for security techniques to protect against malicious modifications, piracy and reverse engineering
  • Describes safeguarding design techniques such as obfuscation, encryption, and watermarking
  • Introduces IP trust metrics and benchmarks and covers state-of-the-art techniques for validation of IP security and trust
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eBook $109.00
price for USA (gross)
  • ISBN 978-3-319-49025-0
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $139.00
price for USA
  • ISBN 978-3-319-49024-3
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.

About the authors

Prabhat Mishra is an Associate Professor in the Department of Computer and Information Science and Engineering (CISE) at the University of Florida (UF) where he leads the CISE Embedded Systems Lab. His research interests include design automation of embedded systems, energy-aware computing, reconfigurable architectures, hardware security and trust, system validation and verification, and post-silicon debug.

He received his B.E. from Jadavpur University, Kolkata in 1994, M.Tech. from the Indian Institute of Technology, Kharagpur in 1996, and Ph.D. from the University of California, Irvine in 2004 -- all in Computer Science and Engineering. Prior to joining University of Florida, he spent several years in various companies including Intel, Motorola, Synopsys and Texas Instruments. He has published four books and more than 100 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, IBM Faculty Award, two best paper awards (VLSI Design 2011 and CODES+ISSS 2003), five best paper nominations (including DAC'09 and DATE'12), and 2004 EDAA Outstanding Dissertation Award from the European Design Automation Association. He has also received the 2007 International Educator of the Year Award from the UF College of Engineering for his international research and teaching contributions.

Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a professor in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 200 publications in peer-reviewed journals and premier conferences and four books (three edited) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009).

Mark M. Tehranipoor is currently the Intel Charles E. Young Professor in Cybersecurity at the Department of Electrical and Computer Engineering, the University of Florida. His current research projects include: hardware security and trust, electronics supply chain security, counterfeit IC detection and prevention, and reliable and testable VLSI design. Prof. Tehranipoor has published over 250 journal articles and refereed conference papers and has given more than 150 invited talks and keynote addresses since 2006. In addition, he has published six books and ten book chapters. His projects are sponsored by both the industry (Semiconductor Research Corporation (SRC), Texas Instruments, Freescale, Comcast, Honeywell, LSI, Mentor Graphics, Juniper, R3Logic, Cisco, Qualcomm, MediaTeck, etc.) and the Government (NSF, ARO, MDA, DOD, AFOSR, DOE, etc.).

Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut.

Prof. Tehranipoor is a Senior Member of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA. He is also a member of Connecticut Academy of Science and Engineering (CASE).

Table of contents (15 chapters)

  • Security and Trust Vulnerabilities in Third-Party IPs

    Mishra, Prabhat (et al.)

    Pages 3-14

  • Security Rule Check

    Nahiyan, Adib (et al.)

    Pages 17-36

  • Digital Circuit Vulnerabilities to Hardware Trojans

    Salmani, Hassan (et al.)

    Pages 37-51

  • Code Coverage Analysis for IP Trust Verification

    Nahiyan, Adib (et al.)

    Pages 53-72

  • Analyzing Circuit Layout to Probing Attack

    Shi, Qihang (et al.)

    Pages 73-98

Buy this book

eBook $109.00
price for USA (gross)
  • ISBN 978-3-319-49025-0
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $139.00
price for USA
  • ISBN 978-3-319-49024-3
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Hardware IP Security and Trust
Editors
  • Prabhat Mishra
  • Swarup Bhunia
  • Mark Tehranipoor
Copyright
2017
Publisher
Springer International Publishing
Copyright Holder
Springer International Publishing AG
eBook ISBN
978-3-319-49025-0
DOI
10.1007/978-3-319-49025-0
Hardcover ISBN
978-3-319-49024-3
Edition Number
1
Number of Pages
XII, 353
Number of Illustrations and Tables
53 b/w illustrations, 78 illustrations in colour
Topics