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Embedded Systems

Debugging Systems-on-Chip

Communication-centric and Abstraction-based Techniques

Authors: Vermeulen, Bart, Goossens, Kees

  • Describes trends in embedded system design that make the design of SOCs complex and error-prone
  • Analyzes four key requirements for debugging a modern, silicon SOC implementation and identifies nine factors that complicate meeting these debug requirements
  • Uses communication control for debugging SOCs, which can be used with most on-chip SOC communication protocols in use today
  • Uses communication control to (re)create a particular transaction order and demonstrates that this is helpful in the localization of errors in a SOC implementation
  • Demonstrates the necessity of extracting locally- and globally-consistent states during SOC debug and guarantees by design that they are so
  • Uses a fast and scalable event distribution interconnect, which connects on-chip monitors and protocol specific instruments)
  • Evaluates benefits and costs of the CSAR approach using six industrial SOC designs and an example SOC model
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eBook $109.00
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  • ISBN 978-3-319-06242-6
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Hardcover $139.00
price for USA
valid through October 16, 2017
  • ISBN 978-3-319-06241-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $139.00
price for USA
  • Customers within the U.S. and Canada please contact Customer Service at 1-800-777-4643, Latin America please contact us at +1-212-460-1500 (Weekdays 8:30am – 5:30pm ET) to place your order.
  • Due: November 4, 2016
  • ISBN 978-3-319-35692-1
  • Free shipping for individuals worldwide
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About this book

This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly. Readers learn step-by-step the key requirements for debugging a modern, silicon SOC implementation, nine factors that complicate this debugging task, and a new debug approach that addresses these requirements and complicating factors. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach is discussed in detail, showing how it helps to meet debug requirements and address the nine, previously identified factors that complicate debugging silicon implementations of SOCs. The authors also derive the debug infrastructure requirements to support debugging of a silicon implementation of an SOC with their CSAR debug approach. This debug infrastructure consists of a generic on-chip debug architecture, a configurable automated design-for-debug flow to be used during the design of an SOC, and customizable off-chip debugger software. Coverage includes an evaluation of the efficiency and effectiveness of the CSAR approach and its supporting infrastructure, using six industrial SOCs and an illustrative, example SOC model. The authors also quantify the hardware cost and design effort to support their approach.
 

About the authors

Bart Vermeulen received his MSc and PhD degrees in Electrical Engineering from the Eindhoven University of Technology in respectively 1997 and 2013. He is currently a Senior Principal in the Central Research and Development organization of NXP Semiconductors, The Netherlands. His research interests include the design, validation and test of robust, distributed architectures for embedded systems. He published 40+ papers and 8 patents.

Kees Goossens received his PhD in Computer Science from the University of Edinburgh in 1993 on hardware verification using embeddings of formal semantics of hardware description languages in proof systems. He worked for Philips/NXP Research from 1995 to 2010 on networks on chip for consumer electronics. He is professor at the Eindhoven University of Technology, where his research focusses on composable, predictable, low-power embedded systems. He published 2 books, 100+ papers and 24 patents.

Table of contents (10 chapters)

  • Introduction

    Vermeulen, Bart (et al.)

    Pages 3-24

  • Post-silicon Debugging of a Single Building Block

    Vermeulen, Bart (et al.)

    Pages 27-35

  • Post-silicon Debugging of Multiple Building Blocks

    Vermeulen, Bart (et al.)

    Pages 37-63

  • CSAR Debug Overview

    Vermeulen, Bart (et al.)

    Pages 67-86

  • On-Chip Debug Architecture

    Vermeulen, Bart (et al.)

    Pages 87-137

Buy this book

eBook $109.00
price for USA (gross)
  • ISBN 978-3-319-06242-6
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $139.00
price for USA
valid through October 16, 2017
  • ISBN 978-3-319-06241-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $139.00
price for USA
  • Customers within the U.S. and Canada please contact Customer Service at 1-800-777-4643, Latin America please contact us at +1-212-460-1500 (Weekdays 8:30am – 5:30pm ET) to place your order.
  • Due: November 4, 2016
  • ISBN 978-3-319-35692-1
  • Free shipping for individuals worldwide
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
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Bibliographic Information

Bibliographic Information
Book Title
Debugging Systems-on-Chip
Book Subtitle
Communication-centric and Abstraction-based Techniques
Authors
Series Title
Embedded Systems
Copyright
2014
Publisher
Springer International Publishing
Copyright Holder
Springer International Publishing Switzerland
eBook ISBN
978-3-319-06242-6
DOI
10.1007/978-3-319-06242-6
Hardcover ISBN
978-3-319-06241-9
Softcover ISBN
978-3-319-35692-1
Series ISSN
2193-0155
Edition Number
1
Number of Pages
XV, 311
Number of Illustrations and Tables
120 b/w illustrations, 7 illustrations in colour
Topics