Instruction Level Parallelism

Authors: Aiken, A., Banerjee, U., Kejariwal, A., Nicolau, A.

  • Presents an unprecedented text, uniquely dedicated to Instruction Level Parallelism (ILP)
  • Provides a detailed examination of ILP architectures
  • Offers practical descriptions of key scheduling algorithms for extracting ILP at compile time
  • Illustrates how algorithms can be applied to streaming computations and compilation for Graphics Processing Units (GPUs)
  • Equips readers with a resourceful and comprehensive bibliography that spans over five decades
see more benefits

Buy this book

eBook $69.99
price for USA (gross)
  • ISBN 978-1-4899-7797-7
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $89.99
price for USA
  • ISBN 978-1-4899-7795-3
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

This book precisely formulates and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.


About the authors

Alex Aiken is the Alcatel-Lucent Professor and the current chair of the Computer Science Department at Stanford. His research interests include most areas of programming languages and compilers and particularly automated methods of analysis for both high performance and high reliability.


Utpal Banerjee has a PhD in mathematics from Carnegie-Mellon University and a PhD in computer science from the University of Illinois at Urbana-Champaign. He has taught at the University of Cincinnati, Arizona State University and the University of Illinois. Dr. Banerjee has served as a research staff member at Honeywell, Fairchild, Control Data and Intel corporations. His current affiliation is with the Department of Computer Science, University of California at Irvine. He has published a number of papers and books on restructuring compilers, including encyclopedia articles and a series of books on loop transformations. He is a fellow of the IEEE and a fellow of the ACM. 


Arun Kejariwal is a Statistical Learning Principal at Machine Zone. He co-founded MZ Research and currently manages a team of research scientists. He is leading the research and development of novel algorithms for fraud detection, anomaly detection in security and operational data. Prior to joining Machine Zone, he was a lead in the Data Fidelity Team at Twitter and open sourced standalone R packages for anomaly detection and breakout detection. He received Ph.D. in Computer Science from UC Irvine and is a Senior Member of IEEE and ACM.


Alexandru Nicolau’s research is in the areas of Parallel Processing/ILP, and Embedded Systems/Design Automation. His interests focus on Computer Performance/power tradeoffs, parallelizing compilers, GPUs. His current work involves collaborations both within and outside UCI, most recently with researchers at Stanford, University of Michigan, UCLA, UCSD as part of a flagship NSF Expedition project, and a separate grant with UIUC. He authored over 300 peer-reviewed papers and several books. He is the Editor-in-Chief of the International Journal of Parallel Processing, and an IEEE Fellow.

Reviews

Table of contents (8 chapters)

Buy this book

eBook $69.99
price for USA (gross)
  • ISBN 978-1-4899-7797-7
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $89.99
price for USA
  • ISBN 978-1-4899-7795-3
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Loading...

Recommended for you

Loading...

Bibliographic Information

Bibliographic Information
Book Title
Instruction Level Parallelism
Authors
Copyright
2016
Publisher
Springer US
Copyright Holder
Springer-Verlag US
eBook ISBN
978-1-4899-7797-7
DOI
10.1007/978-1-4899-7797-7
Hardcover ISBN
978-1-4899-7795-3
Edition Number
1
Number of Pages
XXI, 255
Number of Illustrations and Tables
48 b/w illustrations, 30 illustrations in colour
Topics