High Performance Multi-Channel High-Speed I/O Circuits

1. Front Matter

   Pages i-x

   PDF

2. Introduction

   • Taehyoun Oh, Ramesh Harjani

   Pages 1-9

3. \(2\times 6\) Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process

   • Taehyoun Oh, Ramesh Harjani

   Pages 11-25

4. \(4 \times 12\) Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process

   • Taehyoun Oh, Ramesh Harjani

   Pages 27-46

5. Adaptive XTCR, AGC, and Adaptive DFE Loop

   • Taehyoun Oh, Ramesh Harjani

   Pages 47-67

6. Research Summary and Contributions

   • Taehyoun Oh, Ramesh Harjani

   Pages 69-71

7. Back Matter

   Pages 73-89

   PDF

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

• Analog Circuits and Signal Processing
• Channel Inter-Symbol Interference
• Crosstalk Cancellation and Signal Reutilization
• Crosstalk Channel Modeling
• High-Speed Chip-to-Chip Communications
• Multi-Channel High-Speed I/O Circuits
• Wireless Communication

• Department of ECE, University of Minnesota, Minneapolis, USA

  Taehyoun Oh, Ramesh Harjani

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