Authors:
- Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect
- Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance
- Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management
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Table of contents (11 chapters)
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Front Matter
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Network-on-Chip Design Methodology
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Front Matter
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Suggested Projects
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Front Matter
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About this book
Authors and Affiliations
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Dept of Computer Science and Engineering, Frederick University School of Applied Sciences, Nicosia, Cyprus
Konstantinos Tatas
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Department of Computer Science, National Technical University of Athens, Athens, Greece
Kostas Siozios, Dimitrios Soudris
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Department of Electronic Systems, Royal Institute of Technology, Kista, Sweden
Axel Jantsch
Bibliographic Information
Book Title: Designing 2D and 3D Network-on-Chip Architectures
Authors: Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
DOI: https://doi.org/10.1007/978-1-4614-4274-5
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media New York 2014
Hardcover ISBN: 978-1-4614-4273-8
Softcover ISBN: 978-1-4939-4550-4
eBook ISBN: 978-1-4614-4274-5
Edition Number: 1
Number of Pages: XIII, 265
Number of Illustrations: 65 b/w illustrations, 79 illustrations in colour
Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Processor Architectures