Designing 2D and 3D Network-on-Chip Architectures

Authors: Tatas, K., Siozios, K., Soudris, D., Jantsch, A.

  • Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect  
  • Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance  
  • Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management
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eBook $89.00
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  • ISBN 978-1-4614-4274-5
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  • Immediate eBook download after purchase
Hardcover $119.00
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  • ISBN 978-1-4614-4273-8
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  • Usually dispatched within 3 to 5 business days.
Softcover $119.00
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  • ISBN 978-1-4939-4550-4
  • Free shipping for individuals worldwide
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Rent the ebook  
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About this book

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

Table of contents (11 chapters)

  • Network-on-Chip Technology: A Paradigm Shift

    Tatas, Konstantinos (et al.)

    Pages 3-18

  • NoC Modeling and Topology Exploration

    Tatas, Konstantinos (et al.)

    Pages 19-49

  • Communication Architecture

    Tatas, Konstantinos (et al.)

    Pages 51-96

  • Power and Thermal Effects and Management

    Tatas, Konstantinos (et al.)

    Pages 97-126

  • NoC-Based System Integration

    Tatas, Konstantinos (et al.)

    Pages 127-145

Buy this book

eBook $89.00
price for USA (gross)
  • ISBN 978-1-4614-4274-5
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $119.00
price for USA
  • ISBN 978-1-4614-4273-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $119.00
price for USA
  • ISBN 978-1-4939-4550-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
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Bibliographic Information

Bibliographic Information
Book Title
Designing 2D and 3D Network-on-Chip Architectures
Authors
Copyright
2014
Publisher
Springer-Verlag New York
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4614-4274-5
DOI
10.1007/978-1-4614-4274-5
Hardcover ISBN
978-1-4614-4273-8
Softcover ISBN
978-1-4939-4550-4
Edition Number
1
Number of Pages
XIII, 265
Number of Illustrations and Tables
65 b/w illustrations, 79 illustrations in colour
Topics