An ASIC Low Power Primer

Analysis, Techniques and Specification

Authors: Chadha, Rakesh, Bhasker, J.

  • Starts from the ground-up and explains what power is, how it is measured and how it impacts on the ASIC design process
  • Provides essential information in an easy to read and understand format, using basic examples
  • Explains what power intent is, how to describe it precisely and what techniques can be used to achieve the power intent with the two key standards, the Unified Power Format (UPF) and Common Power Format (CPF)
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  • ISBN 978-1-4614-4271-4
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Hardcover $139.00
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  • ISBN 978-1-4614-4270-7
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  • ISBN 978-1-4899-9150-8
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About this book

This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices.  Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs).  The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent.  From analyzing system power consumption, to techniques that can be employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design.

About the authors

J. Bhasker is a well-known expert in the area of hardware description languages and RTL synthesis. He has been chair of two working groups: the IEEE 1076.6 VHDL Synthesis and the IEEE 1364.1 Verilog Synthesis and was awarded the IEEE Computer Society Outstanding Contribution Award in 2005. He is an architect at eSilicon Corporation responsible for the timing of many complex designs.

 Rakesh Chadha is a CAE and Design Professional with over 25 years experience, including 18 years in project leadership and technical management.  He was responsible for the timing and signal integrity for the Sematech project on Chip Parasitic Extraction and Signal Integrity Verification. He is Director of Design Technology at eSilicon Corporation and is responsible for complex SOC design methodology.

Table of contents (9 chapters)

  • Introduction

    Chadha, Rakesh (et al.)

    Pages 1-7

  • Modeling of Power in Core Logic

    Chadha, Rakesh (et al.)

    Pages 9-26

  • Modeling of Power in IOs and Macro Blocks

    Chadha, Rakesh (et al.)

    Pages 27-44

  • Power Analysis in ASICs

    Chadha, Rakesh (et al.)

    Pages 45-65

  • Design Intent for Power Management

    Chadha, Rakesh (et al.)

    Pages 67-91

Buy this book

eBook $109.00
price for USA (gross)
  • ISBN 978-1-4614-4271-4
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $139.00
price for USA
  • ISBN 978-1-4614-4270-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $139.00
price for USA
  • ISBN 978-1-4899-9150-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
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Bibliographic Information

Bibliographic Information
Book Title
An ASIC Low Power Primer
Book Subtitle
Analysis, Techniques and Specification
Authors
Copyright
2013
Publisher
Springer-Verlag New York
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4614-4271-4
DOI
10.1007/978-1-4614-4271-4
Hardcover ISBN
978-1-4614-4270-7
Softcover ISBN
978-1-4899-9150-8
Edition Number
1
Number of Pages
XIV, 218
Topics