Multi-Net Optimization of VLSI Interconnect

Authors: Moiseev, Konstantin, Kolodny, Avinoam, Wimer, Shmuel

  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization
  • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools
  • Includes mathematical properties and conditions for optimality of layout, describes and analyses algorithmic solutions, and supplements analysis with examples taken from state-of-the-art chips
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eBook $89.00
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  • ISBN 978-1-4614-0821-5
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  • ISBN 978-1-4614-0820-8
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Softcover $119.00
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  • ISBN 978-1-4939-4262-6
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About this book

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.

About the authors

Konstantin Moiseev received the B.Sc., M.Sc. in Computer Engineering and Ph.D. in Electrical Engineering from the Technion – Israel Institute of Technology, Haifa, Israel in 2001, 2006 and 2011, respectively. Since 2006 he has been working with Intel Israel Design Center, Haifa, Israel. His general interests include computer-aided design systems, combinatorial optimization, heursitic methods, VLSI system design and interconnect design.

Avinoam Kolodny is an associate professor of electrical engineering at Technion –Israel Institute of Technology. He joined Intel after completing his doctorate in microelectronics at the Technion in 1980. During twenty years with the company he was engaged in diverse areas including non-volatile memory device physics, electronic design automation and organizational development.  He pioneered static timing analysis of processors, served as Intel’s corporate CAD system architect at the introduction of logic synthesis, and was manager of Intel’s performance verification CAD group in Israel. He has been a member of the Faculty of Electrical Engineering at the Technion since 2000. His current research is focused primarily on interconnect issues in VLSI systems, covering all levels from physical design of wires to networks on chip and multi-core system architecture.

Shmuel Wimer received the B.Sc. and M.Sc. degrees in mathematics from Tel-Aviv University, Tel-Aviv, Israel, and the D.Sc. degree in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in 1978, 1981 and 1988, respectively. He worked for thirty two years at industry in R&D, engineering and managerial positions. From 1999 to 2009 he was with Intel Design Center in Haifa Israel, where he was responsible for the development, implementation and execution of Intel's microprocessors physical layout design migration (aka Tick-Tock). Prior to that, he worked for IBM, National Semiconductor and Israeli Aerospace Industry (IAI). He is presently an Associate Professor with the Engineering Faculty of Bar-Ilan University, and an Associate Visiting Professor with the Electrical Engineering Faculty, Technion. He is interested in VLSI circuits and systems design optimization and combinatorial optimization.

Table of contents (10 chapters)

  • An Overview of the VLSI Interconnect Problem

    Moiseev, Konstantin (et al.)

    Pages 1-9

  • Interconnect Aspects in Design Methodology and EDA Tools

    Moiseev, Konstantin (et al.)

    Pages 11-16

  • Scaling Dependent Electrical Modeling of Interconnects

    Moiseev, Konstantin (et al.)

    Pages 17-34

  • Frameworks for Interconnect Optimization

    Moiseev, Konstantin (et al.)

    Pages 35-42

  • Net-by-Net Wire Optimization

    Moiseev, Konstantin (et al.)

    Pages 43-61

Buy this book

eBook $89.00
price for USA (gross)
  • ISBN 978-1-4614-0821-5
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $119.00
price for USA
  • ISBN 978-1-4614-0820-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $119.00
price for USA
  • ISBN 978-1-4939-4262-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Multi-Net Optimization of VLSI Interconnect
Authors
Copyright
2015
Publisher
Springer-Verlag New York
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4614-0821-5
DOI
10.1007/978-1-4614-0821-5
Hardcover ISBN
978-1-4614-0820-8
Softcover ISBN
978-1-4939-4262-6
Edition Number
1
Number of Pages
XVI, 233
Number of Illustrations and Tables
80 b/w illustrations, 44 illustrations in colour
Topics