Digital System Test and Testable Design

1. Front Matter

   Pages i-xvii

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2. Basics of Test and Role of HDLs

   • Zainalabedin Navabi

   Pages 1-20

3. Verilog HDL for Design and Test

   • Zainalabedin Navabi

   Pages 21-62

4. Fault and Defect Modeling

   • Zainalabedin Navabi

   Pages 63-101

5. Fault Simulation Applications and Methods

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   Pages 103-142

6. Test Pattern Generation Methods and Algorithms

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   Pages 143-174

7. Deterministic Test Generation Algorithms

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   Pages 175-212

8. Design for Test by Means of Scan

   • Zainalabedin Navabi

   Pages 213-259

9. Standard IEEE Test Access Methods

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   Pages 261-294

10. Logic Built-in Self-test

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    Pages 295-344

11. Test Compression

    • Zainalabedin Navabi

    Pages 345-373

12. Memory Testing by Means of Memory BIST

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    Pages 375-391

13. Back Matter

    Pages 393-435

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This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.

• BIST
• BIST Architetures
• Design for Test
• Digital System Test
• Electronic Testing
• Fault Modeling
• Fault Simulation
• HDL
• Hardware Description Language
• Memory Testing
• PLI
• Testable Design
• Zainalabedin

• Dept. Electrical & Computer, Engineering, Worcester Polytechnic Institute, Worcester, USA

  Zainalabedin Navabi

About the Author Dr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1891, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.

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