Low-Power Variation-Tolerant Design in Nanometer Silicon

Editors: Bhunia, Swarup, Mukhopadhyay, Saibal (Eds.)

  • Presents important challenges in nanometer scale integrated circuit design
  • Presents a holistic view of Low-Power Variation-Tolerant Design
  • Covers modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems
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About this book

Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. Coverage includes logic and memory design, modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. •Introduces readers to some of the most important challenges in low-power and variation-tolerant IC design in nanoscale technologies; •Presents a holistic view of Low-Power Variation-Tolerant Design, at different levels of design abstraction, starting from device to circuit, architecture and system; •Offers comprehensive coverage of modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems, micro-architecture, DSP, mixed-signal and FPGAs, including current industrial practices, technology scaling trends, and emerging challenges; •Describes in detail modeling and analysis of different variation effects (die-to-die and within-die, process and temporal) on low-power designs; Includes coverage of ultra low-power and robust sub-threshold design.

Table of contents (12 chapters)

  • Variations: Sources and Characterization

    Bansal, Aditya (et al.)

    Pages 3-39

  • Power Dissipation

    Zhang, Wei (et al.)

    Pages 41-80

  • Effect of Variations and Variation Tolerance in Logic Circuits

    Ghosh, Swaroop

    Pages 83-108

  • Statistical Design of Integrated Circuits

    Sapatnekar, Sachin S.

    Pages 109-149

  • Low-Power and Variation-Tolerant Memory Design

    Mahmoodi, Hamid

    Pages 151-183

Buy this book

eBook $109.00
price for USA (gross)
  • ISBN 978-1-4419-7418-1
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $149.00
price for USA
  • ISBN 978-1-4419-7417-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $149.00
price for USA
  • ISBN 978-1-4899-8157-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
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Bibliographic Information

Bibliographic Information
Book Title
Low-Power Variation-Tolerant Design in Nanometer Silicon
Editors
  • Swarup Bhunia
  • Saibal Mukhopadhyay
Copyright
2011
Publisher
Springer US
Copyright Holder
Springer Science+Business Media, LLC
eBook ISBN
978-1-4419-7418-1
DOI
10.1007/978-1-4419-7418-1
Hardcover ISBN
978-1-4419-7417-4
Softcover ISBN
978-1-4899-8157-8
Edition Number
1
Number of Pages
XV, 440
Topics