Low Power Networks-on-Chip

Editors: Silvano, Cristina, Lajolo, Marcello, Palermo, Gianluca (Eds.)

  • Describes the most important design techniques that have been invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip-based architectures
  • Applies state-of-the-art, low-power design techniques to the design of on-chip networks to demonstrate the methodology of the design of high-speed, low-power connections
  • Offers a single-source reference to the latest research, otherwise available only in disparate journals and conference proceedings
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About this book

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

Table of contents (10 chapters)

  • Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections

    Anders, Mark A. (et al.)

    Pages 3-20

  • Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

    Matsutani, Hiroki (et al.)

    Pages 21-43

  • Adaptive Voltage Control for Energy-Efficient NoC Links

    Ampadu, Paul (et al.)

    Pages 45-69

  • Asynchronous Communications for NoCs

    Golubcovs, Stanislavs (et al.)

    Pages 71-109

  • Application-Specific Routing Algorithms for Low Power Network on Chip Design

    Palesi, Maurizio (et al.)

    Pages 113-150

Buy this book

eBook $109.00
price for USA (gross)
  • ISBN 978-1-4419-6911-8
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $149.00
price for USA
  • ISBN 978-1-4419-6910-1
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $149.00
price for USA
  • ISBN 978-1-4899-9437-0
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Rent the ebook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
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Bibliographic Information

Bibliographic Information
Book Title
Low Power Networks-on-Chip
Editors
  • Cristina Silvano
  • Marcello Lajolo
  • Gianluca Palermo
Copyright
2011
Publisher
Springer US
Copyright Holder
Springer Science+Business Media LLC
eBook ISBN
978-1-4419-6911-8
DOI
10.1007/978-1-4419-6911-8
Hardcover ISBN
978-1-4419-6910-1
Softcover ISBN
978-1-4899-9437-0
Edition Number
1
Number of Pages
XIX, 287
Topics