Generating Hardware Assertion Checkers

For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring

Authors: Boulé, Marc, Zilic, Zeljko

  • Presents an efficient synthesis of assertion checkers for the main assertion languages (PSL and SVA)
  • Covers applications in verification, emulation, post-fabrication debugging, and on-line monitoring with a unique "under-the-hood" view
  • Serves as a missing link between the literature on assertion languages and pre-made checker libraries
  • Details extensive benchmarks and verification of assertion checkers, with examples of real-world circuit checkers
  • Gives comprehensive background information on hardware assertion languages, temporal logic and finite automata
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eBook $139.00
price for USA (gross)
  • ISBN 978-1-4020-8586-4
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $179.00
price for USA
  • ISBN 978-1-4020-8585-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $179.00
price for USA
  • ISBN 978-90-481-7922-0
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.

This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.

The PSL and SVA languages are treated in a unified way, thereby facilitating better learning and usage of the modern assertion languages, with a focus on obtaining the highest performance from assertion checkers.

The obtained checkers are thoroughly benchmarked and verified, while formal proofs using automated reasoning techniques are explained. Included are examples of practical circuits (PCI, AMBA, Wishbone-PIC, CPU Pipeline) and their assertion checker synthesis.

Table of contents (10 chapters)

Buy this book

eBook $139.00
price for USA (gross)
  • ISBN 978-1-4020-8586-4
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $179.00
price for USA
  • ISBN 978-1-4020-8585-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $179.00
price for USA
  • ISBN 978-90-481-7922-0
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Generating Hardware Assertion Checkers
Book Subtitle
For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
Authors
Copyright
2008
Publisher
Springer Netherlands
Copyright Holder
Springer Science+Business Media B.V.
eBook ISBN
978-1-4020-8586-4
DOI
10.1007/978-1-4020-8586-4
Hardcover ISBN
978-1-4020-8585-7
Softcover ISBN
978-90-481-7922-0
Edition Number
1
Number of Pages
XX, 280
Topics