Frontiers in Electronic Testing

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test

Authors: Pavlov, Andrei, Sachdev, Manoj

  • Gives a process-aware perspective on SRAM circuit design and test
  • Provides detailed coverage of SRAM cell stability, stability sensitivity and analytical evaluation of static noise margin
  • Introduces the concept of stability fault modeling
  • Provides an overview of specialized ‘design for testability’ techniques for SRAM stability test
  • Addresses soft-error considerations of SRAM design
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eBook $149.00
price for USA (gross)
  • ISBN 978-1-4020-8363-1
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $199.00
price for USA
  • ISBN 978-1-4020-8362-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $199.00
price for USA
  • ISBN 978-90-481-7855-1
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.

Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

About the authors

Prof. Sachdev has authored several successful books with Springer

Table of contents (6 chapters)

Buy this book

eBook $149.00
price for USA (gross)
  • ISBN 978-1-4020-8363-1
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $199.00
price for USA
  • ISBN 978-1-4020-8362-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $199.00
price for USA
  • ISBN 978-90-481-7855-1
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Book Subtitle
Process-Aware SRAM Design and Test
Authors
Series Title
Frontiers in Electronic Testing
Series Volume
40
Copyright
2008
Publisher
Springer Netherlands
Copyright Holder
Springer Science+Business Media B.V.
eBook ISBN
978-1-4020-8363-1
DOI
10.1007/978-1-4020-8363-1
Hardcover ISBN
978-1-4020-8362-4
Softcover ISBN
978-90-481-7855-1
Series ISSN
0929-1296
Edition Number
1
Number of Pages
XVI, 194
Topics