Network Theory and Applications

Layout Optimization in VLSI Design

Editors: Bing Lu, Ding-Zhu Du, Sapatnekar, S. (Eds.)

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About this book

Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter­ connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti­ mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre­ sented in Chapter 1. To reduce the run time, different interconnect plan­ ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques.

Table of contents (8 chapters)

  • Integrated Floorplanning and Interconnect Planning

    Chen, Hung-Ming (et al.)

    Pages 1-18

  • Interconnect Planning

    Cong, Jason

    Pages 19-44

  • Modern Standard-cell Placement Techniques

    Yang, Xiaojian (et al.)

    Pages 45-87

  • Non-Hanan Optimization for Global VLSI Interconnect

    Hu, Jiang (et al.)

    Pages 89-123

  • Techniques for Timing-Driven Routing

    Lillis, John

    Pages 125-153

Buy this book

eBook $179.00
price for USA (gross)
  • ISBN 978-1-4757-3415-7
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $229.00
price for USA
  • ISBN 978-1-4020-0089-8
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $229.00
price for USA
  • ISBN 978-1-4419-5206-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Layout Optimization in VLSI Design
Editors
  • Bing Lu
  • Ding-Zhu Du
  • S. Sapatnekar
Series Title
Network Theory and Applications
Series Volume
8
Copyright
2001
Publisher
Springer US
Copyright Holder
Springer Science+Business Media Dordrecht
eBook ISBN
978-1-4757-3415-7
DOI
10.1007/978-1-4757-3415-7
Hardcover ISBN
978-1-4020-0089-8
Softcover ISBN
978-1-4419-5206-6
Series ISSN
1568-1696
Edition Number
1
Number of Pages
VIII, 288
Topics