Frontiers in Electronic Testing

Formal Equivalence Checking and Design Debugging

Authors: Shi-Yu Huang, Kwang-Ting (Tim) Cheng

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About this book

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley

Table of contents (11 chapters)

  • Introduction

    Huang, Shi-Yu (et al.)

    Pages 1-14

  • Symbolic Verification

    Huang, Shi-Yu (et al.)

    Pages 17-37

  • Incremental Verification for Combinational Circuits

    Huang, Shi-Yu (et al.)

    Pages 39-60

  • Incremental Verification for Sequential Circuits

    Huang, Shi-Yu (et al.)

    Pages 61-90

  • AQUILA: A Local BDD-based Equivalence Verifier

    Huang, Shi-Yu (et al.)

    Pages 91-109

Buy this book

eBook $149.00
price for USA (gross)
  • ISBN 978-1-4615-5693-0
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $199.00
price for USA
  • ISBN 978-0-7923-8184-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $199.00
price for USA
  • ISBN 978-1-4613-7606-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Formal Equivalence Checking and Design Debugging
Authors
Series Title
Frontiers in Electronic Testing
Series Volume
12
Copyright
1998
Publisher
Springer US
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4615-5693-0
DOI
10.1007/978-1-4615-5693-0
Hardcover ISBN
978-0-7923-8184-6
Softcover ISBN
978-1-4613-7606-4
Series ISSN
0929-1296
Edition Number
1
Number of Pages
XVIII, 229
Topics