The Springer International Series in Engineering and Computer Science

Loop Tiling for Parallelism

Authors: Jingling Xue

Buy this book

eBook $189.00
price for USA (gross)
  • ISBN 978-1-4615-4337-4
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $240.00
price for USA
  • ISBN 978-0-7923-7933-1
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $240.00
price for USA
  • ISBN 978-1-4613-6948-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.
Features and key topics:

  • Detailed review of the mathematical foundations, including convex polyhedra and cones;
  • Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;
  • Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;
  • A complete suite of techniques for generating SPMD code for a tiled loop nest;
  • Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;
  • End-of-chapter references for further reading.
Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.

Table of contents (7 chapters)

Buy this book

eBook $189.00
price for USA (gross)
  • ISBN 978-1-4615-4337-4
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $240.00
price for USA
  • ISBN 978-0-7923-7933-1
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $240.00
price for USA
  • ISBN 978-1-4613-6948-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Loading...

Recommended for you

Loading...

Bibliographic Information

Bibliographic Information
Book Title
Loop Tiling for Parallelism
Authors
Series Title
The Springer International Series in Engineering and Computer Science
Series Volume
575
Copyright
2000
Publisher
Springer US
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4615-4337-4
DOI
10.1007/978-1-4615-4337-4
Hardcover ISBN
978-0-7923-7933-1
Softcover ISBN
978-1-4613-6948-6
Series ISSN
0893-3405
Edition Number
1
Number of Pages
XIX, 256
Topics