Advanced ASIC Chip Synthesis

Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®

Authors: Bhatnagar, Himanshu

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eBook $169.00
price for USA (gross)
  • ISBN 978-0-306-47507-8
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $219.00
price for USA
  • ISBN 978-0-7923-7644-6
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  • Usually dispatched within 3 to 5 business days.
Softcover $219.00
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  • ISBN 978-1-4757-7629-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

Table of contents (13 chapters)

Buy this book

eBook $169.00
price for USA (gross)
  • ISBN 978-0-306-47507-8
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $219.00
price for USA
  • ISBN 978-0-7923-7644-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $219.00
price for USA
  • ISBN 978-1-4757-7629-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Advanced ASIC Chip Synthesis
Book Subtitle
Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®
Authors
Copyright
2002
Publisher
Springer US
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-0-306-47507-8
DOI
10.1007/b117024
Hardcover ISBN
978-0-7923-7644-6
Softcover ISBN
978-1-4757-7629-4
Edition Number
2
Number of Pages
XXVI, 328
Topics