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Static Timing Analysis for Nanometer Designs

A Practical Approach

  • Book
  • © 2009

Overview

Authors:
  1. Rakesh Chadha
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  2. J. Bhasker
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  • Provides a reference for engineers in the field of static timing analysis for semiconductors
  • Discusses the underlying theoretical background as well as in-depth coverage of timing verification using static timing analysis
  • Covers topics such as CMOS logic gates, cell library, timing arcs, waveform slew, and cell capacitance, among others

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Table of contents (10 chapters)

  1. Front Matter

    Pages 1-19
    Download chapter PDF

  2. Introduction

    • J. Bhasker, Rakesh Chadha
    Pages 1-14

  3. STA Concepts

    • J. Bhasker, Rakesh Chadha
    Pages 15-42

  4. Standard Cell Library

    • J. Bhasker, Rakesh Chadha
    Pages 43-100

  5. Interconnect Parasitics

    • J. Bhasker, Rakesh Chadha
    Pages 101-121

  6. Delay Calculation

    • J. Bhasker, Rakesh Chadha
    Pages 123-146

  7. Crosstalk and Noise

    • J. Bhasker, Rakesh Chadha
    Pages 147-177

  8. Configuring the STA Environment

    • J. Bhasker, Rakesh Chadha
    Pages 179-225

  9. Timing Verification

    • J. Bhasker, Rakesh Chadha
    Pages 227-316

  10. Interface Analysis

    • J. Bhasker, Rakesh Chadha
    Pages 317-363

  11. Robust Verification

    • J. Bhasker, Rakesh Chadha
    Pages 365-446

  12. Back Matter

    Pages 447-572
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Keywords

About this book

iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.

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