Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Authors: Mohanty, S.P., Ranganathan, N., Kougianos, E., Patra, P.

  • Discusses high-level synthesis fundamentals
  • Covers power dissipation sources in nano-CMOS transistors
  • Includes information on power reduction fundamentals, specifically peak power reduction, transient power reduction and leakage power reduction
  • Addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies
  • Deals primarily with high-level (architectural or behavioral) leakage
see more benefits

Buy this book

eBook $169.00
price for USA (gross)
  • ISBN 978-0-387-76474-0
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $219.99
price for USA
  • ISBN 978-0-387-76473-3
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $169.99
price for USA
  • ISBN 978-1-4419-4554-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies.  The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level.  At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.

The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including:

• Power Reduction Fundamentals

• Energy or Average Power Reduction

• Peak Power Reduction

• Transient Power Reduction

• Leakage Power Reduction

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.

Table of contents (10 chapters)

  • Introduction

    Mohanty, Saraju P. (et al.)

    Pages 1-3

  • High-Level Synthesis Fundamentals

    Mohanty, Saraju P. (et al.)

    Pages 5-46

  • Power Modeling and Estimation at Transistor and Logic Gate Levels

    Mohanty, Saraju P. (et al.)

    Pages 47-79

  • Architectural Power Modeling and Estimation

    Mohanty, Saraju P. (et al.)

    Pages 81-130

  • Power Reduction Fundamentals

    Mohanty, Saraju P. (et al.)

    Pages 131-162

Buy this book

eBook $169.00
price for USA (gross)
  • ISBN 978-0-387-76474-0
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $219.99
price for USA
  • ISBN 978-0-387-76473-3
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $169.99
price for USA
  • ISBN 978-1-4419-4554-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Loading...

Recommended for you

Loading...

Bibliographic Information

Bibliographic Information
Book Title
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Authors
Copyright
2008
Publisher
Springer US
Copyright Holder
Springer-Verlag US
Distribution Rights
Distribution rights for India: CBS Publishers, New Delhi, India
eBook ISBN
978-0-387-76474-0
DOI
10.1007/978-0-387-76474-0
Hardcover ISBN
978-0-387-76473-3
Softcover ISBN
978-1-4419-4554-9
Edition Number
1
Number of Pages
XXXII, 302
Number of Illustrations and Tables
20 b/w illustrations
Topics