Authors:
- Focuses on the design of SystemVerilog for circuit design engineers
- Includes numerous examples and updates that encorporates key elements of IEEE 1364.2001 standard
- The adopted syntax and recommendations from the standards body are explained
- Includes supplementary material: sn.pub/extras
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Table of contents (12 chapters)
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Front Matter
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Back Matter
About this book
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.
The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.
SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language.
In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.
Authors and Affiliations
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Sutherland DHL, Inc., Tualatin, USA
Stuart Sutherland
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The Old Vicerage Priest End, Thame, Oxfordshire, UK
Simon Davidmann
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Imperas, Ltd., Thame, Oxfordshire, UK
Peter Flake
Bibliographic Information
Book Title: SystemVerilog for Design Second Edition
Book Subtitle: A Guide to Using SystemVerilog for Hardware Design and Modeling
Authors: Stuart Sutherland, Simon Davidmann, Peter Flake
DOI: https://doi.org/10.1007/0-387-36495-1
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2006
Hardcover ISBN: 978-0-387-33399-1Published: 20 July 2006
Softcover ISBN: 978-1-4419-4125-1Published: 29 October 2010
eBook ISBN: 978-0-387-36495-7Published: 15 September 2006
Edition Number: 2
Number of Pages: XXX, 418
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Computer Hardware, Electrical Engineering