Design of Systems on a Chip: Design and Test

Editors: Reis, Ricardo, Soares Lubaszewski, Marcelo, Jess, Jochen A.G. (Eds.)

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About this book

Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.

About the authors

Ricardo Reis is a former president of the Brazilian Computer Society and former vice-president of the Brazilian Microelectronics Society. He is now trustee of both societies. He is a trustee and former vice-president of the International Federation for Information Processing, IFIP. He received the Silver Core Award from IFIP. He is member of IFIP TC10 and WG 10.5. He is the Editor-in-Chief of the Journal of Integrated Circuits and Systems, JICS. Ricardo is also Member of the Editorial Board Latin America liaison of the IEEE D&T as Latin America liaison. He contributed to the organizing and program committees of several a large number of international conferences (like VLSI-SoC, ISVLSI, ISSS+CODES, PATMOS, RAW, LATW, SBCCI, IFIP World Congress, …) and he is a founder of the SBCCI conference series (Symposium on Integrated Circuits and Systems Design). He is also Editor of several books.

Table of contents (4 chapters)

  • Core Architectures for Digital Media and the Associated Compilation Techniques

    Jochen A.G. Jess

    Pages 27-63

  • Behavioral Synthesis: an Overview

    Reinaldo A. Bergamaschi

    Pages 103-131

  • Synthesis of FPGAs and Testable ASICs

    Don W. Bouldin

    Pages 179-210

  • Embedded Core-based System-on-Chip Test Strategies

    Yervant Zorian

    Pages 223-238

Buy this book

eBook $149.00
price for USA (gross)
  • ISBN 978-0-387-32500-2
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $199.00
price for USA
  • ISBN 978-0-387-32499-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $199.00
price for USA
  • ISBN 978-1-4419-4089-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Design of Systems on a Chip: Design and Test
Editors
  • Ricardo Reis
  • Marcelo Soares Lubaszewski
  • Jochen A.G. Jess
Copyright
2007
Publisher
Springer US
Copyright Holder
Springer-Verlag US
eBook ISBN
978-0-387-32500-2
DOI
10.1007/0-387-32500-X
Hardcover ISBN
978-0-387-32499-9
Softcover ISBN
978-1-4419-4089-6
Edition Number
1
Number of Pages
X, 234
Topics