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Designing 2D and 3D Network-on-Chip Architectures

  • Book
  • © 2014

Overview

Authors:
  1. Konstantinos Tatas

    1. Dept of Computer Science and Engineering, Frederick University School of Applied Sciences, Nicosia, Cyprus

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  2. Kostas Siozios

    1. Department of Computer Science, National Technical University of Athens, Athens, Greece

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  3. Dimitrios Soudris

    1. Department of Computer Science, National Technical University of Athens, Athens, Greece

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  4. Axel Jantsch

    1. Department of Electronic Systems, Royal Institute of Technology, Kista, Sweden

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  • Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect
  • Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance
  • Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management

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Table of contents (11 chapters)

  1. Front Matter

    Pages i-xiii
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  2. Network-on-Chip Design Methodology

    1. Front Matter

      Pages 1-1
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    2. Network-on-Chip Technology: A Paradigm Shift

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 3-18

    3. NoC Modeling and Topology Exploration

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 19-49

    4. Communication Architecture

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 51-96

    5. Power and Thermal Effects and Management

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 97-126

    6. NoC-Based System Integration

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 127-145

    7. NoC Verification and Testing

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 147-159

    8. The Spidergon STNoC

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 161-190

    9. Middleware Memory Management in NoC

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 191-208

    10. On Designing 3-D Platforms

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 209-236

    11. The SYSMANTIC NoC Design and Prototyping Framework

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 237-255

  3. Suggested Projects

    1. Front Matter

      Pages 257-257
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    2. Projects on Network-on-Chip

      • Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 259-265
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Keywords

About this book

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

Authors and Affiliations

  • Dept of Computer Science and Engineering, Frederick University School of Applied Sciences, Nicosia, Cyprus

    Konstantinos Tatas

  • Department of Computer Science, National Technical University of Athens, Athens, Greece

    Kostas Siozios, Dimitrios Soudris

  • Department of Electronic Systems, Royal Institute of Technology, Kista, Sweden

    Axel Jantsch

Bibliographic Information

  • Book Title: Designing 2D and 3D Network-on-Chip Architectures

  • Authors: Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

  • DOI: https://doi.org/10.1007/978-1-4614-4274-5

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media New York 2014

  • Hardcover ISBN: 978-1-4614-4273-8

  • Softcover ISBN: 978-1-4939-4550-4

  • eBook ISBN: 978-1-4614-4274-5

  • Edition Number: 1

  • Number of Pages: XIII, 265

  • Number of Illustrations: 65 b/w illustrations, 79 illustrations in colour

  • Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Processor Architectures

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