Theoretical Computer Science and General Issues

A Pipelined Multi-core MIPS Machine

Hardware Implementation and Correctness Proof

Authors: Kovalev, Mikhail, Müller, Silvia Melitta, Paul, Wolfgang J.

  • Demonstrates construction of a multi-core machine with pipelined MIPS processor
  • Broadens the understanding of RISC machines
  • Opens the way to the formal verification of synthesizable hardware for multi-core processors
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eBook 47,59 €
price for Spain (gross)
  • ISBN 978-3-319-13906-7
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  • Immediate eBook download after purchase
Softcover 58,24 €
price for Spain (gross)
  • ISBN 978-3-319-13905-0
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
About this Textbook

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

Table of contents (9 chapters)

Buy this book

eBook 47,59 €
price for Spain (gross)
  • ISBN 978-3-319-13906-7
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover 58,24 €
price for Spain (gross)
  • ISBN 978-3-319-13905-0
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
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Bibliographic Information

Bibliographic Information
Book Title
A Pipelined Multi-core MIPS Machine
Book Subtitle
Hardware Implementation and Correctness Proof
Authors
Series Title
Theoretical Computer Science and General Issues
Series Volume
9000
Copyright
2014
Publisher
Springer International Publishing
Copyright Holder
Springer International Publishing Switzerland
eBook ISBN
978-3-319-13906-7
DOI
10.1007/978-3-319-13906-7
Softcover ISBN
978-3-319-13905-0
Edition Number
1
Number of Pages
XII, 352
Number of Illustrations and Tables
147 b/w illustrations
Topics