Overview
- Editors:
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Manoj Sachdev
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University of Waterloo, Ontario, Canada
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José Pineda de Gyvez
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Philips Research Laboratories, Eindhoven University of Technology, Eindhoven, The Netherlands
- Wide coverage of topics in test engineering
- Unique defect-oriented focus of the materials
- Introduction to yield engineering common practices
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Table of contents (8 chapters)
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- Manoj Sachdev, José Pineda de Gyvez
Pages 1-22
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- Manoj Sachdev, José Pineda de Gyvez
Pages 23-67
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- Manoj Sachdev, José Pineda de Gyvez
Pages 69-110
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- Manoj Sachdev, José Pineda de Gyvez
Pages 111-150
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- Manoj Sachdev, José Pineda de Gyvez
Pages 151-223
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- Manoj Sachdev, José Pineda de Gyvez
Pages 225-287
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- Manoj Sachdev, José Pineda de Gyvez
Pages 289-315
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- Manoj Sachdev, José Pineda de Gyvez
Pages 317-324
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Back Matter
Pages 325-328
About this book
Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.
Editors and Affiliations
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University of Waterloo, Ontario, Canada
Manoj Sachdev
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Philips Research Laboratories, Eindhoven University of Technology, Eindhoven, The Netherlands
José Pineda de Gyvez