Authors:
- Gives a process-aware perspective on SRAM circuit design and test
- Provides detailed coverage of SRAM cell stability, stability sensitivity and analytical evaluation of Static Noise Margin
- Introduces the concept of stability fault modelling
- Provides an Overview of specialized Design for Testability techniques for SRAM stability test
- Addresses soft-error considerations of SRAM design
Part of the book series: Frontiers in Electronic Testing (FRET, volume 40)
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Table of contents (6 chapters)
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Front Matter
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Back Matter
About this book
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
Authors and Affiliations
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Intel Corporation, Hillsboro, USA
Andrei Pavlov
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Dept. Electrical & Computer Engineering, University of Waterloo, N2L 3G1, Waterloo, Canada
Manoj Sachdev
Bibliographic Information
Book Title: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Book Subtitle: Process-Aware SRAM Design and Test
Authors: Andrei Pavlov, Manoj Sachdev
Series Title: Frontiers in Electronic Testing
DOI: https://doi.org/10.1007/978-1-4020-8363-1
Publisher: Springer Dordrecht
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media B.V. 2008
Hardcover ISBN: 978-1-4020-8362-4Published: 21 June 2008
Softcover ISBN: 978-90-481-7855-1Published: 28 October 2010
eBook ISBN: 978-1-4020-8363-1Published: 01 June 2008
Series ISSN: 0929-1296
Edition Number: 1
Number of Pages: XVI, 194
Topics: Circuits and Systems, Memory Structures