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From Contamination to Defects, Faults and Yield Loss

Simulation and Applications

  • Book
  • © 1996

Overview

Authors:
  1. Jitendra B. Khare

    1. Carnegie Mellon University, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  2. Wojciech Maly

    1. Carnegie Mellon University, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

Part of the book series: Frontiers in Electronic Testing (FRET, volume 5)

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-xv
    Download chapter PDF

  2. Introduction

    • Jitendra B. Khare, Wojciech Maly
    Pages 1-12

  3. Background

    • Jitendra B. Khare, Wojciech Maly
    Pages 13-35

  4. Contamination-Defect-Fault (CDF) Simulation

    • Jitendra B. Khare, Wojciech Maly
    Pages 37-46

  5. CDF Mapper Codef

    • Jitendra B. Khare, Wojciech Maly
    Pages 47-83

  6. CODEF - Applications

    • Jitendra B. Khare, Wojciech Maly
    Pages 85-114

  7. Possible Extensions

    • Jitendra B. Khare, Wojciech Maly
    Pages 115-119

  8. Conclusion

    • Jitendra B. Khare, Wojciech Maly
    Pages 121-122

  9. Back Matter

    Pages 123-150
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Keywords

About this book

Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield.
Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing.
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems.
Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.

Authors and Affiliations

  • Carnegie Mellon University, USA

    Jitendra B. Khare, Wojciech Maly

Bibliographic Information

  • Book Title: From Contamination to Defects, Faults and Yield Loss

  • Book Subtitle: Simulation and Applications

  • Authors: Jitendra B. Khare, Wojciech Maly

  • Series Title: Frontiers in Electronic Testing

  • DOI: https://doi.org/10.1007/978-1-4613-1377-9

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Kluwer Academic Publishers 1996

  • Hardcover ISBN: 978-0-7923-9714-4Published: 30 April 1996

  • Softcover ISBN: 978-1-4612-8595-3Published: 26 September 2011

  • eBook ISBN: 978-1-4613-1377-9Published: 06 December 2012

  • Series ISSN: 0929-1296

  • Edition Number: 1

  • Number of Pages: XVI, 150

  • Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design

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