Analysis and VLSI Architecture of High Definition and Scalable VideoCoding Standards
Chen, Liang-Gee, Chen, Yi-Hau
2016, Approx. 250 p.
Springer eBooks may be purchased by end-customers only and are sold without copy protection (DRM free). Instead, all eBooks include personalized watermarks. This means you can read the Springer eBooks across numerous devices such as Laptops, eReaders, and tablets.
You can pay for Springer eBooks with Visa, Mastercard, American Express or Paypal.
After the purchase you can directly download the eBook file or read it online in our Springer eBook Reader. Furthermore your eBook will be stored in your MySpringer account. So you can always re-download your eBooks.
digitally watermarked, no DRM
The eBook version of this title will be available soon
This book addresses the algorithm analysis and VLSI architecture of video encoders, especially for high definition and scalable video coder. The three design challenges and related system issues of memory bandwidth (including system memory and internal memory), hardware area, and power consumption (required operating frequency) are all discussed. With the high definition encoder, the authors focus on algorithm modification and design parallelism to provide high processing capability for the video encoder. Several corresponding hardware schedules are also included to cooperate with proposed architecture. For scalable video coding, the emphasis is placed not only on video algorithms, but also on hardware performance. The algorithm modification, data reuse schemes from frame-level to candidates-level, and architecture design contribute in the developing of three scalabilities and first MCTF hardware design. Finally, the first SVC encoder chip for HDTV1080p is presented and all above design issues are considered together.
Part I: High Definition Video Encoder.- Frame-Parallel Design Strategy for High Definition Video Encoder with B-frame.- Algorithm and Architecture Design for Intra Prediction in H.264/AVC High Profile.- Part II: Scalable Video Coding.- Fast Prediction Algorithm of Adaptive GOP Structure for SVC.- Efficient Architecture Design of Motion.-.Compensated Temporal Filtering/Motion Compensated Prediction Engine.- Cost-Efficient Residual Prediction VLSI Architecture for H.264/AVC Scalable Extension.- Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension.- Part III: HDTV1080p H.264/AVC High Profile and Scalable Extension Encoder Chip.- An H.264/AVC Scalable Extension and High Profile HDTV 1080p Encoder Chip.- Conclusion.