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Unique combination of design, test, debugging and calibration of A/D converters, probably the only one on the market
Numerous examples and easy-to-follow procedures for design, test, debugging and calibration of A/D converters
Provides both state-of-the-art software and hardware implementations as well as their chip realizations
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods.
In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
1. Introduction. 1.1. A/D Conversion Systems. 1.2. Remarks on Curent Design and Debugging Practice. 1.3. Motivation. 1.4. Organization.
2. Analog to Digital Conversion. 2.1. High-Speed High-Resolution A/D Converter Architectural Choices. 2.2. Notes on Low Voltage A/D Converter Design. 2.3. A/D Converter Building Blocks. 2.4. A/D Converters: Summary.
3. Design of Multi-Step Analog to Digital Converters. 3.1. Multi-Step A/D Converter Architecture. 3.2. Deisgn Considerations for Non-Ideal Multi-Step A/D Converter. 3.3. Time-Interleaved Front-End Sample-and-Hold Circuit. 3.4. Multi-Step A/D Converter Stage Design. 3.5. Inter-Stage Design and Calibration. 3.6. Experimental Results. 3.7. Conclusion.
4. Multi-Step Analog to Digital Converter Testing. 4.1. Analog ATPG for Quasi-Static Structural Test. 4.2. Design for Testability Concept. 4.3. On-Chip Stimulus Generation for BIST Applications. 4.4. Remarks on Built-In Self-Test Concepts. 4.5. Stochastic Analysis of Deep-Submicron CMOS Process. 4.5. Conclusion.
5. Multi-Step Analog to Digital Converter Debugging. 5.1. Concept of Sensor Networks. 5.2. Estimation of Die-Level Process Variations. 5.3. Debugging of Multi-Step A/D Converter Stages. 5.4. DfT for Full Accessability of Multi-Step Converters. 5.5. Debugging of Time-Interleaved Systems. 5.6. Foreground Calibration. 5.7. Experimental Results. 5.8. Conclusion.
6. Conclusions and Recommendations. 6.1. Summary of Results. 6.3. Recommendations and Future Research.