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On-Line Testing for VLSI

  • Book
  • © 1998

Overview

Editors:
  1. Michael Nicolaidis

    1. TIMA Laboratories, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. Yervan Zorian

    1. Logic Vision, Inc., USA

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    You can also search for this editor in PubMed   Google Scholar

  3. Dhiraj K. Pradan

    1. Texas A & M University, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Frontiers in Electronic Testing (FRET, volume 11)

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Table of contents (15 chapters)

  1. Front Matter

    Pages 1-5
    Download chapter PDF

  2. Introduction

    1. On-line Testing for VLSI—A Compendium of Approaches

      • M. Nicolaidis, Y. Zorian
      Pages 7-20

  3. Self-Checking Design

    1. On-Line Fault Monitoring

      • J. J. Stiffler
      Pages 21-27

    2. Efficient Totally Self-Checking Shifter Design

      • Ricardo O. Duarte, M. Nicolaidis, H. Bederr, Y. Zorian
      Pages 29-39

    3. A New Design Method for Self-Checking Unidirectional Combinational Circuits

      • V. V. Saposhnikov, A. Morosov, VL. V. Saposhnikov, M. Gössel
      Pages 41-53

    4. Concurrent Delay Testing in Totally Self-Checking Systems

      • Antonis Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis
      Pages 55-61

  4. Self Checking Checkers

    1. Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters

      • Stanisław J. Piestrak
      Pages 63-68

    2. Self-Testing Embedded Two-Rail Checkers

      • Dimitris Nikolos
      Pages 69-79

  5. On-Line Monitoring of Reliability Indicators

    1. Thermal Monitoring of Self-Checking Systems

      • V. Székely, M. Rencz, J. M. Karam, M. Lubaszewski, B. Courtois
      Pages 81-92

    2. Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronic Structures

      • Karim Arabi, Bozena Kaminska
      Pages 93-99

    3. Clocked Dosimeter Compatible with Digital CMOS Technology

      • E. Garcia-Moreno, B. Iñiguez, M. Roca, J. Segura, E. Isern
      Pages 101-110

  6. Built-In Self-Test

    1. Scalable Test Generators for High-Speed Datapath Circuits

      • Hussain Al-Asaad, John P. Hayes, Brian T. Murray
      Pages 111-125

    2. Mixed-Mode BIST Using Embedded Processors

      • Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
      Pages 127-138

    3. A BIST Scheme for Non-Volatile Memories

      • Piero Olivo, Marcello Dalpasso
      Pages 139-144

  8. Back Matter

    Pages 161-161
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Keywords

About this book

Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs.
On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties.
On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.

Editors and Affiliations

  • TIMA Laboratories, USA

    Michael Nicolaidis

  • Logic Vision, Inc., USA

    Yervan Zorian

  • Texas A & M University, USA

    Dhiraj K. Pradan

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