Integrated Circuit Defect-Sensitivity: Theory and Computational Models

1. Front Matter

   Pages i-xxiv

   PDF

2. Introduction

   • José Pineda de Gyvez

   Pages 1-6

3. Defect Semantics and Yield Modeling

   • José Pineda de Gyvez

   Pages 7-27

4. Computational Models for Defect-Sensitivity

   • José Pineda de Gyvez

   Pages 29-47

5. Single Defect Multiple Layer (SDML) Model

   • José Pineda de Gyvez

   Pages 49-78

6. Fault Analysis and Multiple Layer Critical Areas

   • José Pineda de Gyvez

   Pages 79-91

7. Single Defect Single Layer (SDSL) Model

   • José Pineda de Gyvez

   Pages 93-108

8. IC Yield Prediction and Single Layer Critical Areas

   • José Pineda de Gyvez

   Pages 109-124

9. Single vs. Multiple Layer Critical Areas

   • José Pineda de Gyvez

   Pages 125-136

10. Back Matter

    Pages 137-167

    PDF

The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.

• circuit
• design
• electronics
• integrated circuit
• microelectronics
• model
• modeling

• Texas A&M University, USA

  José Pineda Gyvez

Policies and ethics