2009, XII, 288p. 222 illus. in color. With CD-ROM.
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Contains contributed chapters by two renowned design engineers
Low Power Design Essentials is the first book at the graduate level to address the design of low power digital integrated circuits in an orderly and logical fashion. As such, this book will be of interest to students as well as professionals. In addition to taking an educational approach towards low-power design, the book also presents an integrated methodology to address power at all layers of the design hierarchy. Finally, the text also explains the main roadblocks as well as the physical limits in further energy scaling. This book is based on the extensive amount of teaching the author has carried out both at universities and companies worldwide. All chapters have been drawn up specifically for self-study. Different levels of understanding are included within each chapter. All chapters begin with elementary material and almost all contain advanced material. A unique format is used for this book. Rather than the traditional approach of a lengthy continuous text interspersed with some figures, it uses the reverse approach of dominant graphics with accompanying suppplemental text. It is understood that a single figure does a lot more to convey a message than a page of text. It is hoped that this innovative format provides a better structure for learning the essential topics in low power design. About the Author Jan Rabaey received his Ph.D degree in Applied Sciences from the Katholieke Universiteit Leuven, Belgium. From 1983-1985, he was connected to the UC Berkeley as a Visiting Research Engineer. From 1985-1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the FCRP-sponsored GigaScale Systems Research Center (GSRC). He is an IEEE Fellow.
Content Level »Professional/practitioner
Keywords »Ultra-low power and - advanced MOS transistors - digital design - interconnect - logic - low power design methodologies and flows - material - optimizing power at design time - optimizing power at runtime - optimizing power at standby - power management - transistor
Nanometer Transistors and Their Models.- Power and Energy Basics.- Optimizing Power @ Design Time – Circuit-Level Techniques.- Optimizing Power @ Design Time – Architecture, Algorithms, and Systems.- Optimizing Power @ Design Time – Interconnect and Clocks.- Optimizing Power @ Design Time – Memory.- Optimizing Power @ Standby – Circuits and Systems.- Optimizing Power @ Standby – Memory.- Optimizing Power @ Runtime – Circuits and Systems.- Ultra Low Power/Voltage Design.- Low Power Design Methodologies and Flows.- Summary and Perspectives.