Protecting Chips Against Hold Time Violations Due to Variability
Neuberger, Gustavo, Wirth, Gilson, Reis, Ricardo
2014, XI, 107 p. 76 illus., 51 illus. in color.
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Presents a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology
Studies the consequences of variability in several aspects of circuit design
Focuses specifically on the effects of storage elements on circuit design
This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements. The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.
· Provides a comprehensive review of various reliability mechanisms;
· Describes practical modeling and characterization techniques for reliability
· Includes thorough presentation of robust design techniques for major VLSI design units
· Promotes physical understanding with first-principle simulations