VLSI Physical Design: From Graph Partitioning to Timing Closure
Kahng, A.B., Lienig, J., Markov, I.L., Hu, J.
2011, XI, 310 p.
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Offers comprehensive coverage of Physical Design of Integrated Circuits, PCBs and MCMs, and emphasizes practical algorithms and methodologies Includes a chapter on timing closure that includes a discussion of design flows Features detailed illustrations of key concepts, numerous examples Presents brief surveys of recent research results with up-to-date references for further reading Accessible to beginners and students Includes problem sets for students, with solutions
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. VLSI Physical Design: From Graph Partitioning to Timing Closure introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.